A structured, hands-on introduction to digital integrated circuit design using Verilog HDL. Each module builds on the previous, taking you from simple logic gates all the way to finite state machines ...

Writes testbenches, performs functional simulation, and uses methodologies like UVM (Universal Verification Methodology). Skills Needed: SystemVerilog / Verilog Simulation tools (ModelSim, QuestaSim) ...

Analog design should take up half this list, that’s the depth and variety of subject matter that could be done. Students should be aware that coursework is an introduction not a qualification to do ...