IEEE

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Abstract: Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and ...
EDN

Self-correcting codes conquer noise, part one: Viterbi codecs

FEC (forward-error-correction) techniques correct errors at the receiver end of digital communications systems. In contrast with error-detection and retransmission ...
IEEE

A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application

Abstract: Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed ...
Frontiers

Neuromorphic Analog Implementation of Neural Engineering Framework-Inspired Spiking Neuron for High-Dimensional Representation

Brain-inspired hardware designs realize neural principles in electronics to provide high-performing, energy-efficient frameworks for artificial intelligence. The Neural Engineering Framework (NEF) ...
Nature

Implementation of half adder and half subtractor with a simple and universal DNA-based platform

As a powerful material, DNA presents great advantages in the fabrication of molecular devices and higher-order logic circuits. Herein, by making use of the hybridization and displacement of DNA ...